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data sheet, rev. 1 october 2002 FW802C low-power phy ieee ? 1394 a-2000 two-cable transceiver/arbiter device ? distinguishing features n compliant with ieee standard 1394 a-2000, ieee standard for a high performance serial bus amendment 1. n low-power consumption during powerdown or microlow-power sleep mode. n supports extended bias_handshake time for enhanced interoperability with camcorders. n while unpowered and connected to the bus, the device will not drive tpbias on a connected port even if receiving incoming bias voltage on that port. n does not require external filter capacitors for pll. n does not require a separate 5 v supply for 5 v link controller interoperability. n interoperable across 1394 ? cable with 1394 physi- cal layers (phy) using 5 v supplies. n interoperable with 1394 link-layer controllers using 5 v supplies. n 1394 a-2000 compliant common-mode noise filter on incoming tpbias. n powerdown features to conserve energy in battery- powered applications include: device powerdown pin. link interface disable using lps. inactive ports powerdown. automatic microlow-power sleep mode during suspend. n interface to link-layer controller supports annex j electrical isolation as well as bus-keeper isolation. features n provides two compliant cable ports at 100 mbits/s, 200 mbits/s, and 400 mbits/s. n supports ohci requirements. n supports arbitrated short bus reset to improve utilization of the bus. n supports ack-accelerated arbitration and fly-by con- catenation. n supports connection debounce. n supports multispeed packet concatenation. n supports phy pinging and remote phy access packets. n supports full suspend/resume. n supports phy-link interface initialization and reset. n supports 1394 a-2000 register set. n supports lps/link-on as a part of phy-link inter- face. n supports provisions of ieee 1394 -1995 standard for a high performance serial bus . n fully interoperable with firewire ? implementation of ieee 1394 -1995. n reports cable power fail interrupt when voltage at cps pin falls below 7.5 v. n separate cable bias and driver termination voltage supply for each port. n meets intel ? mobile power guideline 2000 . other features n 48-pin tqfp package. n single 3.3 v supply operation. n data interface to link-layer controller provided through 2/4/8 parallel lines at 50 mbits/s. n 25 mhz crystal oscillator and pll provide transmit/ receive data at 100 mbits/s, 200 mbits/s, and 400 mbits/s, and link-layer controller clock at 50 mhz. n node power-class information signaling for system power management. n multiple separate package signals provided for ana- log and digital supplies and grounds.
2 2 agere systems inc. data sheet, rev. 1 october 2002 two-cable transceiver/arbiter device FW802C low-power phy ieee 1394a-2000 table of contents contents page distinguishing features ....................................................................................................... .....................................1 features ...................................................................................................................... .............................................1 other features ................................................................................................................ .........................................1 description ................................................................................................................... .............................................3 signal information ............................................................................................................ .........................................6 application information ....................................................................................................... ....................................10 1394 application support contact information ...................................................................................... .................11 crystal selection considerations .............................................................................................. ..............................11 load capacitance .............................................................................................................. ..............................12 board layout .................................................................................................................. ..................................12 absolute maximum ratings ...................................................................................................... ..............................12 electrical characteristics .................................................................................................... ....................................13 timing characteristics ........................................................................................................ ....................................16 timing waveforms .............................................................................................................. ....................................17 internal register configuration ............................................................................................... ................................18 outline diagrams .............................................................................................................. ......................................23 48-pin tqfp ................................................................................................................... .................................23 ordering information .......................................................................................................... .....................................23 list of figures figures page figure 1. block diagram ....................................................................................................... ................................. 5 figure 2. pin assignments ..................................................................................................... ................................ 6 figure 3. typical external component connections .............................................................................. ............. 10 figure 4. typical port termination network .................................................................................... .................... 11 figure 5. dn, ctln, and lreq input setup and hold times waveforms .......................................................... 17 figure 6. dn, ctln output delay relative to sysclk waveforms .................................................................. .. 17 list of tables tables page table 1. signal descriptions................................................................................................... ................................ 7 table 2. absolute maximum ratings.............................................................................................. ...................... 12 table 3. analog characteristics................................................................................................ ............................ 13 table 4. driver characteristics ................................................................................................ ............................. 14 table 5. device characteristics................................................................................................ ............................ 15 table 6. switching characteristics ............................................................................................. .......................... 16 table 7. clock characteristics ................................................................................................ ............................. 16 table 8. phy register map for the cable environment ........................................................................... ........... 18 table 9. phy register fields for the cable environment ......................................................................... ........... 18 table 10. phy register page 0: port status page ............................................................................... .............. 20 table 11. phy register port status page fields ................................................................................ ................ 21 table 12. phy register page 1: vendor identification page ..................................................................... ......... 22 table 13. phy register vendor identification page fields ...................................................................... ........... 22
data sheet, rev. 1 FW802C low-power phy ieee 1394a-2000 august 2002 two-cable transceiver/arbiter device agere systems inc. 3 description the agere systems inc. FW802C device provides the analog physical layer functions needed to implement a two-port node in a cable-based ieee 1394 -1995 and ieee 1394 a-2000 network. each cable port incorporates two differential line trans- ceivers. the transceivers include circuitry to monitor the line conditions as needed for determining connec- tion status, for initialization and arbitration, and for packet reception and transmission. the phy is designed to interface with a link-layer controller (llc). the phy requires either an external 24.576 mhz crystal or crystal oscillator. the internal oscillator drives an internal phase-locked loop (pll), which generates the required 400 mhz reference signal. the 400 mhz reference signal is internally divided to provide the 49.152 mhz, 98.304 mhz, and 196.608 mhz clock signals that control transmission of the outbound encoded strobe and data information. the 49.152 mhz clock signal is also supplied to the associated llc for synchronization of the two chips and is used for resynchronization of the received data. the powerdown function, when enabled by the pd signal high, stops operation of the pll and disables all circuitry except the cable-not-active signal circuitry. the phy supports an isolation barrier between itself and its llc. when /iso is tied high, the link interface outputs behave normally. when /iso is tied low, internal differentiating logic is enabled, and the outputs become short pulses, which can be coupled through a capacitor or transformer as described in the ieee 1394 -1995 annex j. to operate with bus-keeper isolation, the /iso pin of the FW802C must be tied high. data bits to be transmitted through the cable ports are received from the llc on two, four, or eight data lines (d[0:7]), and are latched internally in the phy in synchronization with the 49.152 mhz system clock. these bits are combined serially, encoded, and transmitted at 98.304 mbits/s, 196.608 mbits/s, or 393.216 mbits/s as the outbound data-strobe information stream. during transmission, the encoded data information is transmitted differentially on the tpa and tpb cable pair(s). during packet reception, the tpa and tpb transmitters of the receiving cable port are disabled, and the receivers for that port are enabled. the encoded data information is received on the tpa and tpb cable pair. the received data-strobe information is decoded to recover the receive clock signal and the serial data bits. the serial data bits are split into two, four, or eight parallel streams, resynchronized to the local system clock, and sent to the associated llc. the received data is also transmitted (repeated) out of the other active (connected) cable ports. both the tpa and tpb cable interfaces incorporate differential comparators to monitor the line states during initialization and arbitration. the outputs of these comparators are used by the internal logic to determine the arbitration status. the tpa channel monitors the incoming cable common-mode voltage. the value of this common-mode voltage is used during arbitration to set the speed of the next packet transmission. in addition, the tpb channel monitors the incoming cable common-mode voltage for the presence of the remotely supplied twisted-pair bias voltage. this monitor is called bias-detect. the tpbias circuit monitors the value of incoming tpa pair common-mode voltage when local tpbias is inactive. because this circuit has an internal current source and the connected node has a current sink, the monitored value indicates the cable connection status. this monitor is called connect-detect. both the tpb bias-detect monitor and tpbias connect-detect monitor are used in suspend/resume signaling and cable connection detection. the phy provides a 1.86 v nominal bias voltage for driver load termination. this bias voltage, when seen through a cable by a remote receiver, indicates the presence of an active connection. the value of this bias voltage has been chosen to allow interoperability between transceiver chips operating from 5 v or 3 v nominal supplies. this bias voltage source should be stabilized by using an external filter capacitor of approximately 0.33 m f. the transmitter circuitry, the receiver circuitry, and the twisted-pair bias voltage circuity are all disabled with a powerdown condition. the powerdown condition occurs when the pd input is high. the port transmitter circuitry, the receiver circuitry, and the tpbias output are also disabled when the port is disabled, suspended, or disconnected. the line drivers in the phy operate in a high- impedance current mode and are designed to work with external 112 w line-termination resistor networks. one network is provided at each end of each twisted- pair cable. each network is composed of a pair of series-connected 56 w resistors. the midpoint of the pair of resistors that is directly connected to the twisted-pair a (tpa) signals is connected to the pbias voltage signal. the midpoint of the pair of
FW802C low-power phy ieee 1394a-2000 data sheet, rev. 1 two-cable transceiver/arbiter device august 2002 4 agere systems inc. description (continued) resistors that is directly connected to the twisted-pair b (tpb) signals is coupled to ground through a parallel rc network with recommended resistor and capacitor values of 5 k w and 220 pf, respectively. the value of the external resistors are specified to meet the standard specifications when connected in parallel with the internal receiver circuits. the driver output current, along with other internal operating currents, is set by an external resistor. this resistor is connected between the r0 and r1 signals and has a value of 2.49 k w 1%. the FW802C supports suspend/resume as defined in the ieee 1394 a-2000 specification. the suspend mechanism allows an FW802C port to be put into a suspended state. in this state, a port is unable to transmit or receive data packets; however, it remains capable of detecting connection status changes and detecting incoming tpbias. when all ports of the FW802C are suspended, all circuits except the bias voltage reference generator and the bias detection circuits are powered down, resulting in significant power savings. the use of suspend/resume is recommended. the signal, c/lkon, as an input, indicates whether a node is a contender for bus manager. when the c/lkon signal is asserted, it means the node is a contender for bus manager. when the signal is not asserted, it means that the node is not a contender. the c bit corresponds to bit 20 in the self-id packet (see table 4-29 of the ieee 1394 -1995 standard for additional details). the power class bits of the self-id packet do not have a default value. these bits can be initialized and read/ written through the llc using figure 6-1 (phy register map) of the ieee 1394 a-2000 standard. see table 8 for the address space of the pwr_class register. a powerdown signal (pd) is provided to allow a powerdown mode where most of the phy circuits are powered down to conserve energy in battery-powered applications. the internal logic in FW802C is reset as long as the powerdown signal is asserted. a cable status signal, cna, provides a high output when none of the twisted-pair cable ports are receiving incoming bias voltage. this output is not debounced. the cna output can be used to determine when to power the phy down or up. in the powerdown mode, all circuitry is disabled except the cna circuitry. it should be noted that when the device is powered down, it does not act in a repeater mode. when the power supply of the phy is removed while the twisted-pair cables are connected, the phy transmitter and receiver circuitry has been designed to present a high impedance to the cable in order to not load the tpbias signal voltage on the other end of the cable. for reliable operation, the tpbn signals must be terminated using the normal termination network regardless of whether a cable is connected to a port or not connected to a port. for those applications, when FW802C is used with one of the ports not brought out to a connector, those unused ports may be left unconnected without normal termination. when a port does not have a cable connected, internal connect- detect circuitry will keep the port in a disconnected state. note: all gap counts on all nodes of a 1394 bus must be identical. this may be accomplished by using phy configuration packets (see section 4.3.4.3 of ieee 1394 -1995 standard) or by using two bus resets, which resets the gap counts to the maximum level (3fh). the link power status (lps) signal works with the c/lkon signal to manage the llc power usage of the node. the lps signal indicates that the llc of the node is powered up or powered down. if lps is inac- tive for more than 1.2 m s and less than 25 m s, phy/link interface is reset. if lps is inactive for greater than 25 m s, the phy will disable the phy/link interface to save power. FW802C continues its repeater function. if the phy then receives a link-on packet, the c/lkon signal is activated to output a 6.114 mhz signal, which can be used by the llc to power itself up. once the llc is powered up, the lps signal communicates this to the phy and the phy/link interface is enabled. c/lkon signal is turned off when lps is active or when a bus reset occurs, provided the interrupt that caused c/lkon is not present. when the phy/link interface is in the disabled state, the FW802C will automatically enter a low-power mode, if all ports are inactive (disconnected, disabled, or suspended). in this low-power mode, the FW802C disables its pll and also disables parts of reference circuitry depending on the state of the ports (some ref- erence circuitry must remain active in order to detect incoming tp bias). the lowest power consumption (the microlow-power sleep mode) is attained when all ports are either disconnected or disabled with the ports inter- rupt enable bit cleared. the FW802C will exit the low- power mode when the lps input is asserted high or when a port event occurs that requires the FW802C
data sheet, rev. 1 FW802C low-power phy ieee 1394a-2000 august 2002 two-cable transceiver/arbiter device agere systems inc. 5 description (continued) to become active in order to respond to the event or to notify the llc of the event (e.g., incoming bias or dis- connection is detected on a suspended port, a new connection is detected on a nondisabled port, etc.). the sysclk output will become active (and the phy/ link interface will be initialized and become operative) within 3 ms after lps is asserted high, when the FW802C is in the low-power mode. two of the signals are used to set up various test conditions used in manufacturing. these signals (se and sm) should be connected to v ss for normal operation. 5-5459.f (f) figure 1. block diagram link interface i/o received data decoder/ arbitration and control retimer state machine logic bias voltage and current generator cable port 1 oscillator, pll system, and clock generator transmit data encoder cable port 0 tpa0+ tpa0C tpb0+ tpb0C tpbias0 tpbias1 tpa1+ tpa1C tpb1+ tpb1C xi xo cps lps /iso cna sysclk lreq ctl0 ctl1 d0 d1 d2 d3 c/lkon se sm pd /reset crystal d4 d5 d6 d7 r0 r1
6 6 agere systems inc. data sheet, rev. 1 october 2002 two-cable transceiver/arbiter device FW802C low-power phy ieee 1394a-2000 signal information note: active-low signals are indicated by / at the beginning of signal names, within this document. 5-6236.b (f) figure 2. pin assignments 12 11 10 9 8 6 5 4 3 2 1 7 agere FW802C v ss d7 d6 d5 d4 d2 v dd d1 d0 ctl1 ctl0 d3 25 26 27 28 29 31 32 33 34 35 36 30 tpb0C tpb0+ tpa0C tpa0+ tpbias0 tpb1C tpb1+ tpa1C tpa1+ tpbias1 v ssa v dda 37 38 39 40 41 43 44 45 46 47 48 42 r0 r1 v dd v ss pllv dd xi xo /reset sysclk v ss lreq pllv ss 13 14 15 16 17 19 20 21 22 23 24 18 cna lps v ss v dd c/lkon /iso cps se sm v dda v ssa pd pin #1 identifier
agere systems inc. 7 data sheet, rev. 1 october 2002 two-cable transceiver/arbiter device FW802C low-power phy ieee 1394a-2000 signal information (continued) table 1. signal descriptions pin signal * type name/description 17 c/lkon i/o bus manager capable input and link-on output. on hardware reset, this pin is used to set the default value of the contender status indicated during self-id. the bit value programming is done by tying the signal through a 10 k w resistor to v dd (high, bus manager capable) or to gnd (low, not bus manager capable). using either the pull-up or pull-down resistor allows the link-on output to override the input value when neces- sary. after hardware reset, this pin is set as an output. if the lps is inactive, c/lkon indicates one of the following events by asserting a 6.114 mhz signal. 1. FW802C receives a link-on packet addressed to this node. 2. port_event register bit is 1. 3. any of the timeout, pwr_fail, or loop register bits are 1 and the resume_int register bit is also 1. once activated, the c/lkon output will continue active until the lps becomes active. the phy also deas- serts the c/lkon output when a bus reset occurs, if the c/lkon is active due solely to the reception of a link-on packet. note: if an interrupt condition exists that would otherwise cause the c/lkon output to be activated if the lps were inactive, the c/lkon output will be activated when the lps subsequently becomes inactive. 13 cna o cable-not-active output. cna is asserted high when none of the phy ports are receiving an incoming bias voltage. this circuit remains active during the powerdown mode. 20 cps i cable power status. cps is normally connected to the cable power through a 400 k w resistor. this circuit drives an internal comparator that detects the presence of cable power. this information is maintained in one internal register and is available to the llc by way of a register read (see table 8, register 0). 1 ctl0 i/o control i/o. the ctln signals are bidirectional communications control signals between the phy and the llc. these signals control the passage of information between the two devices. bus-keeper circuitry is built into these terminals. 2ctl1 3, 4, 6, 7, 8, 9, 10, 11 d[0:7] i/o data i/o. the dn signals are bidirectional and pass data between the phy and the llc. bus-keeper circuitry is built into these terminals. 19 /iso i link interface isolation disable input (active-low). /iso controls the operation of an internal pulse differentiating function used on the phy-llc interface signals, ctln and dn, when they operate as outputs. when /iso is asserted low, the isolation barrier is implemented between phy and its llc (as described in annex j of ieee 1394 -1995). /iso is normally tied high to disable isolation differentiation. bus-keepers are enabled when /iso is high (inactive) on ctl, d, and lreq. when /iso is low (active), the bus-keepers are disabled. please refer to ageres application note ap98-074cmpr for more information on isolation. * active-low signals are indicated by / at the beginning of signal names, within this document.
8 8 agere systems inc. data sheet, rev. 1 october 2002 two-cable transceiver/arbiter device FW802C low-power phy ieee 1394a-2000 signal information (continued) table 1. signal descriptions (continued) pin signal * type name/description 14 lps i link power status. lps is connected to either the v dd supplying the llc or to a pulsed output that is active when the llc is powered for the purpose of monitoring the llc power status. if lps is inactive for more than 1.2 m s and less than 25 m s, interface is reset. if lps is inactive for greater than 25 m s, the phy will disable the phy/link interface to save power. FW802C continues its repeater function. 48 lreq i link request. lreq is an output from the llc that requests the phy to perform some service. bus-keeper circuitry is built into this terminal. 18 pd i powerdown. when asserted high, pd turns off all internal circuitry except the bias-detect circuits that drive the cna signal. internal FW802C logic is kept in the reset state as long as pd is asserted. pd terminal is provided for backward compatibility. it is recommended that the FW802C be allowed to manage its own power consumption using suspend/resume in conjunction with lps. c/lkon features are defined in 1394 a-2000. 41 pllv dd power for pll circuit. pllv dd supplies power to the pll circuitry portion of the device. 42 pllv ss ground for pll circuit. pllv ss is tied to a low-impedance ground plane. 37 r0 i current setting resistor. an internal reference voltage is applied to a resistor connected between r0 and r1 to set the operating current and the cable driver output current. a low temperature-coefficient resistor (tcr) with a value of 2.49 k w 1% should be used to meet the ieee 1394 -1995 standard requirements for output voltage limits. 38 r1 45 /reset i reset (active-low). when /reset is asserted low (active), the FW802C is reset. an internal pull-up resistor, which is connected to v dd , is provided, so only an external delay capacitor is required. this input is a standard logic buffer and can also be driven by an open-drain logic output buffer. 21 se i test mode control. se is used during the manufacturing test and should be tied to v ss . 22 sm i test mode control. sm is used during the manufacturing test and should be tied to v ss . 46 sysclk o system clock. sysclk provides a 49.152 mhz clock signal, which is synchronized with the data transfers to the llc. 28 tpa0+ analog i/o portn, port cable pair a. tpan is the port a connection to the twisted- pair cable. board traces from each pair of positive and negative differen- tial signal pins should be kept matched and as short as possible to the external load resistors and to the cable connector. 34 tpa1+ 27 tpa0 - analog i/o portn, port cable pair a. tpan is the port a connection to the twisted- pair cable. board traces from each pair of positive and negative differen- tial signal pins should be kept matched and as short as possible to the external load resistors and to the cable connector. 33 tpa1 - 26 tpb0+ analog i/o portn, port cable pair b. tpbn is the port b connection to the twisted- pair cable. board traces from each pair of positive and negative differen- tial signal pins should be kept matched and as short as possible to the external load resistors and to the cable connector. 32 tpb1+ * active-low signals are indicated by / at the beginning of signal names, within this document.
agere systems inc. 9 data sheet, rev. 1 october 2002 two-cable transceiver/arbiter device FW802C low-power phy ieee 1394a-2000 25 tpb0 - analog i/o portn, port cable pair b. tpbn is the port b connection to the twisted- pair cable. board traces from each pair of positive and negative differen- tial signal pins should be kept matched and as short as possible to the external load resistors and to the cable connector. 31 tpb1 - 29 tpbias0 analog i/o portn, twisted-pair bias. tpbias provides the 1.86 v nominal bias voltage needed for proper operation of the twisted-pair cable drivers and receivers and for sending a valid cable connection signal to the remote nodes. 35 tpbias1 5, 16, 39 v dd digital power. v dd supplies power to the digital portion of the device. 23, 30 v dda analog circuit power. v dda supplies power to the analog portion of the device. 12, 15, 40, 47 v ss digital ground. all v ss signals should be tied to the low-impedance ground plane. 24, 36 v ssa analog circuit ground. all v ssa signals should be tied together to a low- impedance ground plane. 43 xi crystal oscillator. xi and xo connect to a 24.576 mhz parallel resonant fundamental mode crystal. although, when a 24.576 mhz clock source is used, it can be connected to xi with xo left unconnected. the optimum values for the external shunt capacitors are dependent on the specifica- tions of the crystal used. for more details, see crystal selection consider- ations in the application information section. 44 xo signal information (continued) table 1. signal descriptions (continued) pin signal * type name/description * active-low signals are indicated by / at the beginning of signal names, within this document.
10 10 agere systems inc. data sheet, rev. 1 october 2002 two-cable transceiver/arbiter device FW802C low-power phy ieee 1394a-2000 application information 5-6767 (f) * see figure 4 for typical port termination network. figure 3. typical external component connections 12 11 10 9 8 6 5 4 3 2 1 7 agere FW802C v ss d7 d6 d5 d4 d2 v dd d1 d0 ctl1 ctl0 d3 25 26 27 28 29 31 32 33 34 35 36 30 tpb0C tpb0+ tpa0C tpa0+ tpbias0 tpb1C tpb1+ tpa1C tpa1+ tpbias1 v ssa v dda 37 38 39 40 41 43 44 45 46 47 48 42 r0 r1 v dd v ss pllv dd xi xo /reset sysclk v ss lreq pllv ss 13 14 15 16 17 19 20 21 22 23 24 18 cna lps v ss v dd c/lkon /iso cps se sm v dda v ssa pd pin #1 identifier 24.576 mhz 0.1 m f 2.49 k w 510 k w port 1* port 0* cable power 400 k w
data sheet, rev. 1 FW802C low-power phy ieee 1394a-2000 august 2002 two-cable transceiver/arbiter device agere systems inc. 11 application information (continued) 5-6930 (f) figure 4. typical port termination network 1394 application support contact information e-mail: support1394@agere.com crystal selection considerations the FW802C is designed to use an external 24.576 mhz crystal connected between the xi and xo terminals to provide the reference for an internal oscillator circuit. ieee 1394 a-2000 standard requires that FW802C have less than 100 ppm total variation from the nominal data rate, which is directly influenced by the crystal. to achieve this, it is recommended that an oscillator with a nominal 50 ppm or less frequency tolerance be used. the total frequency variation must be kept below 100 ppm from nominal with some allowance for error introduced by board and device variations. trade offs between frequency tolerance and stability may be made as long as the total frequency variation is less than 100 ppm. tpbias1 tpa1+ tpa1C tpb1+ tpb1C tpbias0 tpa0+ tpa0C tpb0+ tpb0C 35 34 33 32 31 29 28 27 26 25 tpbias1 56 w 56 w 56 w 56 w 5 k w 220 pf 0.33 m f ieee 1394 -1995 standard connector use same port termination network as illustrated below. 1 3 5 2 4 6 vg vp cable power
12 12 agere systems inc. data sheet, rev. 1 october 2002 two-cable transceiver/arbiter device FW802C low-power phy ieee 1394a-2000 crystal selection considerations (continued) load capacitance the frequency of oscillation is dependent upon the load capacitance specified for the crystal, in parallel resonant mode crystal circuits. total load capacitance (c l ) is a function of not only the discrete load capacitors, but also capacitances from the FW802C board traces and capacitances of the other FW802C connected components. the values for load capacitors (c a and c b ) should be calculated using this formula: c a = c b = (c l C c stray ) 2 where: c l = load capacitance specified by the crystal manufacturer c stray = capacitance of the board and the FW802C, typically 23 pf board layout the layout of the crystal portion of the phy circuit is important for obtaining the correct frequency and minimizing noise introduced into the FW802C pll. the crystal and two load capacitors should be considered as a unit during layout. they should be placed as close as possible to one another, while minimizing the loop area created by the combination of the three components. minimizing the loop area minimizes the effect of the resonant current that flows in this resonant circuit. this layout unit (crystal and load capacitors) should then be placed as close as possi- ble to the phy xi and xo terminals to minimize trace lengths. vias should not be used to route the xi and xo sig- nals. absolute maximum ratings stresses in excess of the absolute maximum ratings can cause permanent damage to the device. these are abso- lute stress ratings only. functional operation of the device is not implied at these or any other conditions in excess of those given in the operational sections of the data sheet. exposure to absolute maximum ratings for extended periods can adversely affect device reliability. table 2. absolute maximum ratings * except for 5 v tolerant i/o (ctl0, ctl1, d0d7, and lreq) where v i max = 5.5 v. parameter symbol min max unit supply voltage range v dd 3.0 3.6 v input voltage range* v i - 0.5 v dd + 0.5 v output voltage range at any output v o - 0.5 v dd + 0.5 v operating free air temperature t a 070 c storage temperature range t stg C65 150 c
agere systems inc. 13 data sheet, rev. 1 october 2002 two-cable transceiver/arbiter device FW802C low-power phy ieee 1394a-2000 electrical characteristics table 3. analog characteristics parameter test conditions symbol min typ max unit supply voltage source power node v ddsp 3.0 3.3 3.6 v differential input voltage cable inputs, 100 mbits/s operation v id100 142 260 mv cable inputs, 200 mbits/s operation v id200 132 260 mv cable inputs, 400 mbits/s operation v id400 100 260 mv cable inputs, during arbitration v idarb 168 265 mv common-mode voltage source power mode tpb cable inputs, speed signaling off v cm 1.165 2.515 v tpb cable inputs, s100 speed signaling on v cmsp100 1.165 2.515 v tpb cable inputs, s200 speed signaling on v cmsp200 0.935 2.515 v tpb cable inputs, s400 speed signaling on v cmsp400 0.532 2.515 v common-mode voltage nonsource power mode* * for a node that does not source power (see section 4.2.2.2 in ieee 1394 -1995 standard). tpb cable inputs, speed signaling off v cm 1.165 2.015 v tpb cable inputs, s100 speed signaling on v cmnsp100 1.165 2.015 v tpb cable inputs, s200 speed signaling on v cmnsp200 0.935 2.015 v tpb cable inputs, s400 speed signaling on v cmnsp400 0.532 2.015 v receive input jitter tpa, tpb cable inputs, 100 mbits/s operation 1.08ns tpa, tpb cable inputs, 200 mbits/s operation 0.5ns tpa, tpb cable inputs, 400 mbits/s operation 0.315ns receive input skew between tpa and tpb cable inputs, 100 mbits/s operation 0.8ns between tpa and tpb cable inputs, 200 mbits/s operation 0.55ns between tpa and tpb cable inputs, 400 mbits/s operation 0.5ns positive arbitration comparator input threshold voltage v th +89168mv negative arbitration comparator input threshold voltage v th - C168 C89 mv speed signal input threshold voltage 200 mbits/s v ths200 45 139 mv 400 mbits/s v ths400 266 445 mv output current tpbias outputs i o C5 2.5 ma tpbias output voltage at rated i/o current v o 1.665 2.015 v current source for connect detect circuit i cd 76 m a
14 14 agere systems inc. data sheet, rev. 1 october 2002 two-cable transceiver/arbiter device FW802C low-power phy ieee 1394a-2000 electrical characteristics (continued) table 4. driver characteristics parameter test conditions symbol min typ max unit differential output voltage 56 w load v od 172 265mv off-state common-mode voltage drivers disabled v off 20mv driver differential current, tpa+, tpa - , tpb+, tpb - driver enabled, speed signaling off* * limits are defined as the algebraic sum of tpa+ and tpa - driver currents. limits also apply to tpb+ and tpb - as the algebraic sum of driver currents. ? limits are defined as the absolute limit of each of tpb+ and tpb - driver currents. i diff - 1.05 1.05ma common-mode speed signaling current, tpb+, tpb - 200 mbits/s speed signaling enabled ? i sp - 2.53 - 4.84 ma 400 mbits/s speed signaling enabled ? i sp - 8.1 - 12.4 ma
agere systems inc. 15 data sheet, rev. 1 october 2002 two-cable transceiver/arbiter device FW802C low-power phy ieee 1394a-2000 electrical characteristics (continued) table 5. device characteristics * device is capable of both differentiated and undifferentiated operation. parameter test conditions symbol min typ max unit supply current: one port active all ports active microlow-power sleep mode pd = 1 v dd = 3.3 v i dd i dd i dd i dd 54 74 50 50 ma ma m a m a high-level output voltage i oh max, v dd = min v oh v dd C 0.4 v low-level output voltage i ol min, v dd = max v ol 0.4v high-level input voltage cmos inputs v ih 0.7v dd v low-level input voltage cmos inputs v il 0.2v dd v pull-up current, /reset input v i = 0 v i i 11 32 m a powerup reset time, /reset input v i = 0 v 2 ms rising input threshold voltage /reset input vi rst 1.1 1.4 v output current sysclk i ol /i oh @ ttl C16 16 ma control, data i ol /i oh @ cmos C12 12 ma cna i ol /i oh C16 16 ma c/lkon i ol /i oh C2 2 ma input current, lreq, lps, pd, se, sm, pc[0:2] inputs v i = v dd or 0 v i i 1 m a off-state output current, ctl[0:1], d[0:7], c/lkon i/os v o = v dd or 0 v i oz 5 m a power status input threshold voltage, cps input 400 k w resistor v th 7.5 8.5 v rising input threshold voltage*, lreq, ctln, dn v it +v dd /2 + 0.3 v dd /2 + 0.8 v falling input threshold voltage*, lreq, ctln, dn v it - v dd /2 C 0.8 v dd /2 C 0.3 v bus holding current, lreq, ctln, dn v i = 1/2(v dd ) 250 550 m a rising input threshold voltage lps v lih 0.24v dd + 1 v falling input threshold voltage lps v lil 0.24v dd + 0.2 v
16 16 agere systems inc. data sheet, rev. 1 october 2002 two-cable transceiver/arbiter device FW802C low-power phy ieee 1394a-2000 timing characteristics table 6. switching characteristics table 7. clock characteristics symbol parameter measured test conditions min typ max unit jitter, transmit tpa, tpb 0.15 ns transmit skew between tpa and tpb 0.1 ns t r rise time, transmit (tpa/tpb) 10% to 90% r i = 56 w, c i = 10 pf 1.2ns t f fall time, transmit (tpa/tpb) 90% to 10% r i = 56 w, c i = 10 pf 1.2ns t su setup time, dn, ctln, lreq - to sysclk - 50% to 50% see figure 5. 6 ns t h hold time, dn, ctln, lreq - from sysclk - 50% to 50% see figure 5. 0 ns t d delay time, sysclk - to dn, ctln - 50% to 50% see figure 6. 1 6 ns parameter symbol min typ max unit external clock source frequency f 24.5735 24.5760 24.5785 mhz
agere systems inc. 17 data sheet, rev. 1 october 2002 two-cable transceiver/arbiter device FW802C low-power phy ieee 1394a-2000 timing waveforms 5-6017.a (f) figure 5. dn, ctln, and lreq input setup and hold times waveforms 5-6018.a (f) figure 6. dn, ctln output delay relative to sysclk waveforms sysclk dn, ctln, lreq tsu th sysclk dn, ctln td
18 18 agere systems inc. data sheet, rev. 1 october 2002 two-cable transceiver/arbiter device FW802C low-power phy ieee 1394a-2000 internal register configuration the phy register map is shown below in table 8. table 8. phy register map for the cable environment the meaning of the register fields within the phy register map are defined by table 9 below. power reset values not specified are resolved by the operation of the phy state machines subsequent to a power reset. table 9. phy register fields for the cable environment address contents bit 0 bit 1 bit 2 bit 3 bit 4 bit 5 bit 6 bit 7 0000 2 physical_id r ps 0001 2 rhb ibr gap_count 0010 2 extended (7) xxxxx to ta l _ p o r ts 0011 2 max_speed xxxxx delay 0100 2 lctrl contender jitter pwr_class 0101 2 resume_int isbr loop pwr_fail timeout port_event enab_accel enab_multi 0110 2 xxxxx xxxxx xxxxx xxxxx xxxxx xxxxx xxxxx xxxxx 0111 2 page_select xxxxx port_select 1000 2 register 0 page_select 1111 2 register 7 page_select required xxxxx reserved field size type power reset value description physical_id 6 r 000000 the address of this node determined during self-identification. a value of 63 indicates a malconfigured bus; the link will not transmit any packets. r 1 r 0 when set to one, indicates that this node is the root. ps 1 r cable power active. rhb 1 rw 0 root hold-off bit. when set to one, the force_root variable is true, which instructs the phy to attempt to become the root during the next tree identify process. ibr 1 rw 0 initiate bus reset. when set to one, instructs the phy to set ibr true and reset_time to reset_time. these values, in turn, cause the phy to initiate a bus reset without arbitration; the reset signal is asserted for 166 m s. this bit is self-clearing. gap_count 6 rw 3f 16 used to configure the arbitration timer setting in order to optimize gap times according to the topology of the bus. see section 4.3.6 of ieee standard 1394 -1995 for the encoding of this field. extended 3 r 7 this field has a constant value of seven, which indicates the extended phy register map.
agere systems inc. 19 data sheet, rev. 1 october 2002 two-cable transceiver/arbiter device FW802C low-power phy ieee 1394a-2000 internal register configuration (continued) table 9. phy register fields for the cable environment (continued) field size type power reset value description total_ports 4 r 2 the number of ports implemented by this phy. this count reflects the number. max_speed 3 r 010 2 indicates the speed(s) this phy supports: 000 2 = 98.304 mbits/s 001 2 = 98.304 and 196.608 mbits/s 010 2 = 98.304, 196.608, and 393.216 mbits/s 011 2 = 98.304, 196.608, 393.216, and 786.43 mbits/s 100 2 = 98.304, 196.608, 393.216, 786.432, and 1,572.864 mbits/s 101 2 = 98.304, 196.608, 393.216, 786.432, 1,572.864, and 3,145.728 mbits/s all other values are reserved for future definition. delay 4 r 0000 worst-case repeater delay, expressed as 144 + (delay * 20) ns. lctrl 1 rw 1 link active. cleared or set by software to control the value of the l bit transmitted in the nodes self-id packet 0, which will be the logical and of this bit and lps active. contender 1 rw see description. cleared or set by software to control the value of the c bit transmitted in the self-id packet. powerup reset value is set by c/lkon pin. jitter 3 r 000 the difference between the fastest and slowest repeater data delay, expressed as (jitter + 1) * 20 ns. pwr_class 3 rw see description. power class. controls the value of the pwr field transmitted in the self-id packet. see section 4.3.4.1 of ieee standard 1394 - 1995 for the encoding of this field. resume_int 1 rw 0 resume interrupt enable. when set to one, the phy will set port_event to one if resume operations commence for any port. isbr 1 rw 0 initiate short (arbitrated) bus reset. a write of one to this bit instructs the phy to set isbr true and reset_time to short_reset_time. these values, in turn, cause the phy to arbitrate and issue a short bus reset. this bit is self-clearing. loop 1 rw 0 loop detect. a write of one to this bit clears it to zero. pwr_fail 1 rw 1 cable power failure detect. set to one when the ps bit changes from one to zero. a write of one to this bit clears it to zero. timeout 1 rw 0 arbitration state machine time-out. a write of one to this bit clears it to zero (see max_arb_state_time). port_event 1 rw 0 port event detect. the phy sets this bit to one if any of con- nected, bias, disabled, or fault change for a port whose int_enable bit is one. the phy also sets this bit to one if resume operations commence for any port and resume_int is one. a write of one to this bit clears it to zero.
20 20 agere systems inc. data sheet, rev. 1 october 2002 two-cable transceiver/arbiter device FW802C low-power phy ieee 1394a-2000 internal register configuration (continued) table 9. phy register fields for the cable environment (continued) the port status page is used to access configuration and status information for each of the phys ports. the port is selected by writing zero to page_select and the desired port number to port_select in the phy register at address 0111 2 . the format of the port status page is illustrated by table 10 below; reserved fields are shown shaded. the meanings of the register fields with the port status page are defined by table 11. table 10. phy register page 0: port status page field size type power reset value description enab_accel 1 rw 0 enable arbitration acceleration . when set to one, the phy will use the enhancements specified in clause 8.11 of 1394 a-2000 specification. phy behavior is unspecified if the value of enab_accel is changed while a bus request is pending. enab_multi 1 rw 0 enable multispeed packet concatenation . when set to one, the link will signal the speed of all packets to the phy. page_select 3 rw 000 selects which of eight possible phy register pages are accessible through the window at phy register addresses 1000 2 through 1111 2 , inclusive. port_select 4 rw 000 if the page selected by page_select presents per-port information, this field selects which ports registers are accessible through the window at phy register addresses 1000 2 through 1111 2 , inclusive. ports are numbered monotonically starting at zero, p0. address contents bit 0 bit 1 bit 2 bit 3 bit 4 bit 5 bit 6 bit 7 1000 2 astat bstat child connected bias disabled 1001 2 negotiated_speed int_enable fault xxxxx xxxxx xxxxx 1010 2 xxxxx xxxxx xxxxx xxxxx xxxxx xxxxx xxxxx xxxxx 1011 2 xxxxx xxxxx xxxxx xxxxx xxxxx xxxxx xxxxx xxxxx 1100 2 xxxxx xxxxx xxxxx xxxxx xxxxx xxxxx xxxxx xxxxx 1101 2 xxxxx xxxxx xxxxx xxxxx xxxxx xxxxx xxxxx xxxxx 1110 2 xxxxx xxxxx xxxxx xxxxx xxxxx xxxxx xxxxx xxxxx 1111 2 xxxxx xxxxx xxxxx xxxxx xxxxx xxxxx xxxxx xxxxx required xxxxx reserved
agere systems inc. 21 data sheet, rev. 1 october 2002 two-cable transceiver/arbiter device FW802C low-power phy ieee 1394a-2000 internal register configuration (continued) the meaning of the register fields with the port status page are defined by table 11 below. table 11. phy register port status page fields field size type power reset value description astat 2 r tpa line state for the port: 00 2 = invalid 01 2 = 1 10 2 = 0 11 2 = z bstat 2 r tpb line state for the port (same encoding as astat). child 1 r 0 if equal to one, the port is a child; otherwise, a parent. the meaning of this bit is undefined from the time a bus reset is detected until the phy transitions to state t1: child hand- shake during the tree identify process (see section 4.4.2.2 in ieee standard 1394 -1995). connected 1 r 0 if equal to one, the port is connected. bias 1 r 0 if equal to one, incoming tpbias is detected. disabled 1 rw 0 if equal to one, the port is disabled. negotiated_speed 3 r 000 indicates the maximum speed negotiated between this phy port and its immediately connected port; the encoding is the same as for the phy register max_speed field. int_enable 1 rw 0 enable port event interrupts. when set to one, the phy will set port_event to one if any of connected, bias, disabled, or fault (for this port) change state. fault 1 rw 0 set to one if an error is detected during a suspend or resume operation. a write of one to this bit clears it to zero.
22 22 agere systems inc. data sheet, rev. 1 october 2002 two-cable transceiver/arbiter device FW802C low-power phy ieee 1394a-2000 internal register configuration (continued) the vendor identification page is used to identify the phys vendor and compliance level. the page is selected by writing one to page_select in the phy register at address 0111 2 . the format of the vendor identification page is shown in table 12; reserved fields are shown shaded. table 12. phy register page 1: vendor identification page the meaning of the register fields within the vendor identification page are defined by table 13. table 13. phy register vendor identification page fields the vendor-dependent page provides access to information used in manufacturing test of the FW802C. address contents bit 0 bit 1 bit 2 bit 3 bit 4 bit 5 bit 6 bit 7 1000 2 compliance_level 1001 2 xxxxx xxxxx xxxxx xxxxx xxxxx xxxxx xxxxx xxxxx 1010 2 1011 2 vendor_id 1100 2 1101 2 1110 2 product_id 1111 2 required xxxxx reserved field size type description compliance_level 8 r standard to which the phy implementation complies: 0 = not specified 1 = ieee 1394 a-2000 ageres FW802C compliance level is 1. all other values reserved for future standardization. vendor_id 24 r the company id or organizationally unique identifier (oui) of the manufacturer of the phy. ageres vendor id is 00601d 16 . this number is obtained from the ieee registration authority committee (rac). the most significant byte of vendor_id appears at phy register location 1010 2 and the least significant at 1100 2 . product_id 24 r the meaning of this number is determined by the company or organization that has been granted vendor_id. ageres FW802C product id is 080201 16 . the most significant byte of product_id appears at phy register location 1101 2 and the least significant at 1111 2 .
agere systems inc. 23 data sheet, rev. 1 october 2002 two-cable transceiver/arbiter device FW802C low-power phy ieee 1394a-2000 outline diagrams 48-pin tqfp dimensions are in millimeters . 5-3080 (f) ordering information device code package comcode FW802C-db 48-pin tqfp 700032322 pin #1 identifier zone 24 7.00 0.20 1 48 37 12 13 36 25 9.00 0.20 7.00 0.20 1.60 max seating plane detail a 0.08 1.40 0.05 0.50 typ 0.05/0.15 detail b detail b 0.19/0.27 0.08 m 0.106/0.200 detail a 0.45/0.75 gage plane seating plane 1.00 ref 0.25 9.00 0.20
agere systems inc. reserves the right to make changes to the product(s) or information contained herein without notice. no liab ility is assumed as a result of their use or application. agere, agere systems, and the agere logo are trademarks of agere systems inc. copyright ? 2002 agere systems inc. all rights reserved october 2002 ds02-362cmpr-1 for additional information, contact your agere systems account manager or the following: internet: http://www.agere.com e-mail: docmaster@agere.com n. america: agere systems inc., lehigh valley central campus, room 10a-301c, 1110 american parkway ne, allentown, pa 18109-9138 1-800-372-2447 , fax 610-712-4106 (in canada: 1-800-553-2448 , fax 610-712-4106) asia: agere systems hong kong ltd., suites 3201 & 3210-12, 32/f, tower 2, the gateway, harbour city, kowloon tel. (852) 3129-2000 , fax (852) 3129-2020 china: (86) 21-5047-1212 (shanghai), (86) 755-25881122 (shenzhen) japan: (81) 3-5421-1600 (tokyo), korea: (82) 2-767-1850 (seoul), singapore: (65) 6778-8833 , taiwan: (886) 2-2725-5858 (taipei) europe: tel. (44)1344 296 400 ieee is a registered trademark and 1394 is a trademark of the institute of electrical and electronics engineers, inc. the firewire logo is a trademark of apple computer, inc. intel is a registered trademark of intel corporation.

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